A typical programmable logic device (PLD) uses conventional N-type metal oxide semiconductor (NMOS) or complementary metal oxide semiconductor (CMOS) transistors. Control voltages within the PLD cause the NMOS or CMOS transistors to turn on or off, thus providing programmable circuitry within the PLD.
Like many other electronic devices, supply voltages for typical PLDs have tended to decrease. The decreased supply voltages often accompany higher speeds of operation and lower power dissipation. The trend towards decreased supply voltages, however, has tended to make the operation of pass transistors and, therefore, the operation of the overall PLD, less reliable.
As the supply voltage decreases, transistors within the PLD (for example, NMOS pass transistors) have increasing difficulty in transmitting a logic 1 (i.e., logic high) level. With sufficiently small power-supply voltages, the pass transistors fail to reliably transmit a logic 1 level, thus causing circuit failure. This problem becomes even more acute in situations where the PLD includes the cascade of several transistors, such as several pass transistors in series. A need therefore exists for transistors that can reliably transmit both binary logic levels (i.e., both logic 0 and logic 1 levels) in PLDs, even with relatively small power-supply voltages.